VerifWorks activities around DVCon USA 2016

VerifWorks, an innovative, women-led, EDA start-up from India is proud to be associated with DVCon in several ways. First of all, our co-founder and Verification technologist Srini will be delivering an danced UVM tutorial at the event. This tutorial is sponsored by Accellera and is shared among 2 EDA companies (VerifWorks & Synopsys) and a high profile trainer (Doug Perry). Srivatsa from Synopsys (as part of his Accellera & IEEE standardization role) will present a preview of changes being done to current UVM 1.2 on its way to become IEEE standard (as of now IEEE P1800.2). Doug will focus on debugging and resolving tricky compile time issues with UVM and touch upon advanced topics such as Factory, config-db etc. Srini will focus on run time tips and tricks with special emphasis on debug hints when unexpected things occur in a UVM simulation. Extracted directly from various customer engagements over the years, the VerifWorks’ contents will be compelling for most UVM enthusiasts who have spent some time with this complex methodology. Srini has also served as a reviewer in DVCon US 2016 TPC team.

On our products side, we have released a new version of our DVCreate series for SystemVerilog interface, UVM (DVC_SVI & DVC_UVM – version 2016.02. The significant updates include:


  1. Flexible clock definitions in the generated System Verilog interface file
  2. A ready to use template testbench with DUT and interface instantiated and a simple clock generator.


  1. Better adherence to coding styles (extern methods, named association etc.)
  2. Run scripts for all major EDA tools

Another exciting product in the making is DVRules ( – industry’s first and only, dynamic UVM rule checker for SystemVerilog-UVM testbenches. The modern approach on this rule checker leaves behind years of known “script based syntax/style checks” (a la “linter”) to do more run time, in-database check via reflection API. We presented this at DVCon India 2015 with huge applause from the audience and have been adding more, top notch rules to it since then. Still in close customer engagements, we hope to fund it enough to see the public deployment later in 2016.

VerifWorks also added RTGen ( – a test generator that recreates a pass/fail test from an available dump file. This is being deployed at real customer use cases especially with Formal Verification (Model checkers) to replay witness traces in simulation world for better debug, regressions etc. We also announced RTGen Traces ( as “apps” on top of RTGen tool to capture industry standard protocol traces from specifications and make them available as tests to use for any IP development on day-1.

Feel free to spot our team at DVCon US in case you are attending via email (srini @ – you may also setup a prior meeting during the first week of March 3-6 (included by filling the form at: Meet-up with VerifWorks at DVCon US ).

Looking forward to seeing you all at DVCon USA 2016!

Posted in DVC_SVI, EDA, SystemVerilog, Uncategorized, UVM.