VerifWorks’s activities around DVCon India 2016

It is that time of the year – when the DV (Design & Verification) community comes together to share ideas, success stories and new products; yes DVCon India 2016 is around the corner. Our co-founder Ajeetha has been running a successful countdown to this mega event for second year in a row @ VerifNews DVCon India 2016 – curtain raiser.

Our team at VerifWorks have been busy during the last few quarters working closely with customers and spending quality time at R&D to develop, release and deploy new solutions and methodologies. This year is special for our VerifWorks team as we have established as the most trusted partner for UVM consulting in India. We have a paper along with our valued customer NXP:

Partitioning for easier reuse of UVM benches – learnings from the trenches  (DVCon IN day-2 papers UVM). In this paper our consulting experts share their experience of optimla design partitioning leading to better verification reuse with UVM. Demystifying the general hype around UVM that “reuse is in-built”, we show with case study what it takes to keep the sequences reusable across levels of verification. A must to attend for all those using UVM for IP, subsystem verification and looking to reuse IP level investments to higher levels. Another important area we touch upon in this paper is the use of RAL models and callbacks to handle safety critical applications. Download extended abstract of this exciting paper below: [wpfilebase tag=file id=45 /].

The other key focus for us at VerifWorks is our own methodology development and we are glad to release an open-source layer around standard UVM named Go2UVM. Being involved with UVM since its early days of development and having deployed at several hundred customer sites (through consulting, training etc.) our team has learnt the pain-points of first-time UVM users. While Go2UVM has been in production use at limited customer sites for over a year, recently we created a dedicated portal to promote and deploy Go2UVM through examples, tutorials, papers and free training sessions. We strongly encourage our readers to visit to learn more. As part of our EDA development we have created several “apps” to automate UVM template generation. All these apps shall be open-sourced around DVCon India 2016. Our team will be presenting this open-source approach along with apps and results as a detailed paper. You can view the abstract here. [wpfilebase tag=file id=46 /]

We are also working on several other “apps” to automate several DV tasks. Meet us at the DVCon India event to learn more. Schedule a meeting with our team via this short form:

Posted in EDA, SystemVerilog, UVM.