Meet us at DVCon-EU 2016 in Munich, Germany Oct 19-20

For many VLSI design & verification engineers DVCon is one of the most awaited industry events. Our team has been contributing, attending, presenting and exhibiting at many DVCon events across the globe. As early as DVCon 2007 our founders have presented a tutorial at DVCon USA. Our executive team worked with global Accellera partners to bring this event to India back in 2014. Coming into 2016, our team was at the DVCon US 2016 event to co-present an advanced UVM tutorial. Slides of the same can be freely downloaded from: Advanced UVM tutorial (from DVCon US 2016) slides now available

Then with the DVCon India 2016 edition, our team had 3 papers and 1 poster on the technical front. We also ran a popular countdown series for the 2016 edition at our partner news site VerifNews.

Now to complete the world-wide journey of DVCon and our team together – we will be at the upcoming DVCon Europe 2016 event at Munich on Oct 19-20.


At the upcoming DVCon Europe event, below is what we’ve planned for:

So overall it will be a big European launch for us at DVCon-EU 2016. In case you are attending the event, please do stop by our booth and stand a chance to win some great gifts!



Posted in EDA, Events, SystemVerilog, UVM.