Mar 23, 2018, Bangalore, India – VerifWorks has joined Accellera Systems Initiative as a member company. This is a key step in promoting upcoming standards such as IEEE 1800.2 UVM, UPF 3.0 and beyond, Portable Stimulus Standard (PSS), IP-XACT and variants – just to name a few. The latest […]
Category Archives: EDA
Meet us at DVCon-EU 2016 in Munich, Germany Oct 19-20
For many VLSI design & verification engineers DVCon is one of the most awaited industry events. Our team has been contributing, attending, presenting and exhibiting at many DVCon events across the globe. As early as DVCon 2007 our founders have presented a tutorial at DVCon USA. Our executive team worked with global Accellera partners to […]
VerifWorks’s activities around DVCon India 2016
It is that time of the year – when the DV (Design & Verification) community comes together to share ideas, success stories and new products; yes DVCon India 2016 is around the corner. Our co-founder Ajeetha has been running a successful countdown to this mega event for second year in a row @ VerifNews DVCon […]
VerifWorks activities around DVCon USA 2016
VerifWorks, an innovative, women-led, EDA start-up from India is proud to be associated with DVCon in several ways. First of all, our co-founder and Verification technologist Srini will be delivering an danced UVM tutorial at the event. This tutorial is sponsored by Accellera and is shared among 2 EDA companies (VerifWorks & Synopsys) and a […]
VerifWorks is among the Top-25 innovators!
As we close a very successful year 2015, a great news for our entire team at VerifWorks and partners – we are chosen as one of the Top 25 innovators in the category of start-ups! As an alma matter of the prestigious Indian Institute of Technology, Delhi (IITD), our co-founder and chief technologist Srini has been […]
More automation rolled out in DVC_SVI
For all SystemVerilog enthusiasts and engineers working day-in and day-out with this powerful language, here is some more reason to cheer! Our latest 2015.10 version of DVCreate SystemVerilog Interface just got better! We now added more automation including: SystemVerilog Interface With modports, clocking blocks Top level Testbench skeleton code DUT instantiation Interface instantiation Clock generation […]
Verdi’s open debug platform enables portability across EDA vendors
Verdi’s open debug platform enables portability across EDA vendors Verdi, the industry’s de-facto debug platform, offers a fully extensible platform for SoC teams and third-party EDA vendors to develop innovative applications (apps) for the large Design & Verification community. VerifWorks (http://www.verifworks.com), a CVC venture has joined the VC Apps program in 2014 and have been […]
Bluepearl’s smart SystemVerilog RTL analysis flags design error early, fast
Recently a smart engineer at Maxim Integrated Circuits asked a tricky question on operator ordering/precedence in an online UVM forum. Though the question originated from UVM/TB code, the similar situation could easily occur in RTL design. Here is a code snippet: Does SystemVerilog standard specify the order in which logical and bit-wise operations get […]
An ACE visualizer for your design’s clocking structure – welcome to Bluepearl’s ACE!
Recently Blue Pearl Software announced the availability of a new feature named ACE – Advanced Clock Environment (http://www.bluepearlsoftware.com/ace/ ). We at VerifWorks tried it on one of our existing DSP designs. The design is not very complex, but it has multiple clock domains, as the core clock is faster than the Enqueue and Dequeue logic. […]
A CDC 101 – what’s metastability & Clock Domain Crossing?
As we bring Blue Pearl’s advanced design verification solutions to India, let’s share the knowledge on the problems being addressed using these products. Here, in this article we leverage on Blue Pearl’s introductory article. Quoting straight from http://www.bluepearlsoftware.com/ace/ At its most basic level, metastability is what happens within a register when data changes too soon before or after […]