For all SystemVerilog enthusiasts and engineers working day-in and day-out with this powerful language, here is some more reason to cheer! Our latest 2015.10 version of DVCreate SystemVerilog Interface just got better! We now added more automation including:
- SystemVerilog Interface
- With modports, clocking blocks
- Top level Testbench skeleton code
- DUT instantiation
- Interface instantiation
- Clock generation with parameterized clock generator
- Template stimulus block to add user’s own stimulus
All of this made available under a push button – given a top level RTL file. Here are some recent benchmarks obtained using our DVC_SVI tool (with previous version). On an average we generate 3X lines of code as many I/O ports you have in your design. For e.g. in the chart below for a USB core with 38 signals at port list, we generate 131 lines of high quality, SystemVerilog code (which otherwise you will have to write manually).
