Avalon AIP

The Avalon®  interface family defines interfaces appropriate for streaming high-speed data, reading and writing registers and memory, and controlling off-chip devices. Avalon® interfaces simplify system design by allowing you to easily connect components in an Altera® FPGA.

VerifWorks team during its various consulting engagements has verified Avalon interface for select customers. As a by product we developed an assertion IP that could serve a wider customer base. Our Avalon AIP is a set of protocol checks extracted from Altera’s Avalon interface specification. They are coded in SystemVerilog Assertions and can be run in simulation and formal verification (ongoing development).



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