More automation rolled out in DVC_SVI

For all SystemVerilog enthusiasts and engineers working day-in and day-out with this powerful language, here is some more reason to cheer! Our latest 2015.10 version of DVCreate SystemVerilog Interface just got better! We now added more automation including: SystemVerilog Interface With modports, clocking blocks Top level Testbench skeleton code DUT instantiation Interface instantiation Clock generation […]

Verdi’s open debug platform enables portability across EDA vendors

Verdi’s open debug platform enables portability across EDA vendors Verdi, the industry’s de-facto debug platform, offers a fully extensible platform for SoC teams and third-party EDA vendors to develop innovative applications (apps) for the large Design & Verification community. VerifWorks (http://www.verifworks.com), a CVC venture has joined the VC Apps program in 2014 and have been […]

Bluepearl’s smart SystemVerilog RTL analysis flags design error early, fast

Recently a smart engineer at Maxim Integrated Circuits asked a tricky question on operator ordering/precedence in an online UVM forum. Though the question originated from UVM/TB code, the similar situation could easily occur in RTL design. Here is a code snippet:   Does SystemVerilog standard specify the order in which logical and bit-wise operations get […]