Hardware design specifications contain waveforms (or) timing diagrams to describe the key signal values and the timing relationships among other signals. Such a diagram is key to understand, decipher and comply to during the design process and a quality verification should ensure such a compliance. However, typical “Timing Diagram” in a spec is non-executable and is usually just an image drawn using some editor. Riding on the success of our indigenous RTGen technology, we at VerifWorks have captured some of the popular specification diagrams in a waveform format and converted that to an executable code in various flavors such as:
- Verilog
- SystemVerilog
- UVM
- VHDL etc.
Below a snapshot of RTGen Trace for a typical AHB-Lite specification
As of now we have the following titles supported with more traces being added:
