Wishbone VIP & AIP

Wishbone is a popular, opensource interface that is heavily found in many of the OpenCores.org designs. Given the momentum around the opensource initiatives, VerifWorks has developed Verification IP around this protocol. We offer the following:

  • Plain SystemVerilog, class based VIP
  • UVM based WB Master VIP
  • WB Master Assertion IP
  • WB Slave Assertion IP

More details on this soon.

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