The Elixir-SV is a comprehensive SystemVerilog Test Suite devloped by VerifWorks (http://www.verifworks.com), a CVC venture. It is aimed at slashing validation time for EDA vendors by assisting in their tool development cycle. It also enables the semiconductor design teams (and/or CAD teams) to qualify and evaluate competing EDA tools thereby avoiding costly redesigns and re-spins. Overall from a mangement perspective Elixir-SV dramatically reduces our customers’ validation effort, costs and time-to-market. SV Test Suite addresses the needs of EDA tool developers to quickly measure the quality of their products. Elixir-SV is a comprehensive test suite based on SystemVerilog IEEE 1800-2005 standard. It is also being upgraded to include SystemVerilog IEEE 1800-2009 and 1800-2012 revisions based on customer demand. Incorporation of these standards in the design cycle will enable semiconductor design teams to create solutions that make designers more efficient.