DVRules – Rules for the Design-Verification

Design-Verification (DV) is a challenging task. While almost anyone can write a DV code (call it TestBench – TB), very few get it right first time. Consider the question:

“Who will verify the code that’s supposed to verify the DUT“?

There fits our DVRules product, an indigenous, built from scratch EDA tool that ensures engineers’ DV code is adhering to the well established rules of the DV domain. We at VerifWorks have a long history of conducting various DVAudits (Auditing users’ DV code) in languages such as e, Vera, SystemC, SystemVerilog, Verilog & VHDL. DVRules is an automation of this time tested process. We have several flavours of this product line in our roadmap:

  • DVR_UVM – our flagship, DVRules product that targets UVM code and verifies the quality of users’ UVM code.
  • DVR_SVA – Rules for the SystemVerilog Assertions code (SVA)
  • DVR_LP – Rules for the Low Power DV environment (UPF)

As with our other products such as DVCreate, DVRules is architected in a portable manner so that we can run on many platforms such as SV simulator, Python etc.


Our native UVM implementation of DVR_UVM is available for free use (including commercial use) till end of 2015. Our “native” implementation allows users to use their favourite EDA tool and add our innovative product on top. Download our DVR_UVM for Mentor Graphics’ Questa simulator here

For other EDA tools, contact us via