Design-Verification (DV) is a challenging task. While almost anyone can write a DV code (call it TestBench – TB), very few get it right first time. Consider the question:
“Who will verify the code that’s supposed to verify the DUT“?
There fits our Karuta product, an indigenous, built from scratch EDA tool that ensures engineers’ DV code is adhering to the well established rules of the DV domain. We at VerifWorks have a long history of conducting various DVAudits (Auditing users’ DV code) in languages such as e, Vera, SystemC, SystemVerilog, Verilog & VHDL. Karuta is an automation of this time tested process. We have several flavours of this product line in our roadmap:
- DVR_UVM – our flagship, Karuta product that targets UVM code and verifies the quality of users’ UVM code.
- DVR_SVA – Rules for the SystemVerilog Assertions code (SVA)
- DVR_LP – Rules for the Low Power DV environment (UPF)