Problem statement:

Given RTL top description, create a SystemVerilog interface

SystemVerilog interfaces:

  • Powerful abstraction technique
  • Most recommended way to connect SV/UVM TB to RTL/DUT
  • Encapsulates communication across TB-DUT
  • Group signals
  • modport, clocking block
  • Assertions
  • Covergroups, cover properties
  • Mundane task to hand-code for every block  

Verdi_1         arrow    VW_DVC_SVI        


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