{"version":"20150408","show_thumbnails":false,"show_date":true,"show_context":true,"layout":"grid","headline":"Related","items":[{"id":36,"url":"http:\/\/verifworks.com\/2014\/08\/an-ace-visualizer-for-your-designs-clocking-structure-welcome-to-bluepearls-ace\/","url_meta":{"origin":34,"position":0},"title":"An ACE visualizer for your design\u2019s clocking structure \u2013 welcome to Bluepearl\u2019s ACE!","date":"August 14, 2014","format":false,"excerpt":"Recently Blue Pearl Software announced the availability of a new feature named ACE \u2013 Advanced Clock Environment (http:\/\/www.bluepearlsoftware.com\/ace\/ ). We at VerifWorks tried it on one of our existing DSP designs. The design is not very complex, but it has multiple clock domains, as the core clock is faster than\u2026","rel":"nofollow","context":"In \"CDC\"","img":{"src":"","width":0,"height":0},"classes":[]},{"id":428,"url":"http:\/\/verifworks.com\/2016\/02\/verifworks-activities-around-dvcon-usa-2016\/","url_meta":{"origin":34,"position":1},"title":"VerifWorks activities around DVCon USA 2016","date":"February 25, 2016","format":false,"excerpt":"VerifWorks, an innovative, women-led, EDA start-up from India is proud to be associated with DVCon in several ways. First of all, our co-founder and Verification technologist Srini will be delivering an danced UVM tutorial at the event. This tutorial is sponsored by Accellera and is shared among 2 EDA companies\u2026","rel":"nofollow","context":"In \"DVC_SVI\"","img":{"src":"","width":0,"height":0},"classes":[]},{"id":381,"url":"http:\/\/verifworks.com\/2015\/10\/more-automation-rolled-out-in-dvc_svi\/","url_meta":{"origin":34,"position":2},"title":"More automation rolled out in DVC_SVI","date":"October 17, 2015","format":false,"excerpt":"For all SystemVerilog enthusiasts and engineers working day-in and day-out with this powerful language, here is some more reason to cheer! Our latest 2015.10 version of DVCreate SystemVerilog Interface just got better! We now added more automation including: SystemVerilog Interface With modports, clocking blocks Top level Testbench skeleton code DUT\u2026","rel":"nofollow","context":"In \"DVC_SVI\"","img":{"src":"","width":0,"height":0},"classes":[]}]}